1. Field of the Invention
The present invention relates to a semiconductor device with a clad type SOI substrate, in which a high voltage element and other element are provided in such a manner that those elements are insulated by each other.
2. Description of the Related Art
One of the conventionally known semiconductor devices of the type to which the present invention is directed is disclosed in Japanese Unexamined Patent Publication (Kokai) No. Heisei 4-29353. A fabrication process disclosed in the above-identified publication is illustrated in FIGS. 1A to 1D.
At first, as shown in FIG. 1A, on the surface of a first single crystal silicon substrate 21, a step 21a is formed by a reactive ion etching (RIE) method. Subsequently, over the entire surface of the substrate 21, a silicon dioxide layer 22 is formed by way of a thermal oxidation, a low temperature CVD and so forth.
Then, as shown in FIG. 1B, the surface is abraded by lapping, polishing and other methods to remove the stepped upper portion of the silicon dioxide layer 22 with the stepped lower portion remaining. Thus, a substrate with a flat surface is formed.
Subsequently, as shown in FIG. 1C, a second single crystal silicon substrate 23 is clad on the first substrate 21 and firmly bonded through heat treatment. Then, the second single crystal silicon substrate is abraded up to a predetermined thickness.
Thereafter, as shown in FIG. 1D, V-shaped isolation grooves 24 reaching to the silicon dioxide layer 22 are formed on the surface of the second single crystal silicon substrate 23 to isolate an island, single crystal silicon region 23a. Thereafter, on the surface of the isolation grooves 24, silicon dioxide layer 25 is formed. Then, by providing polycrystalline silicon regions 26 filling the isolation grooves 24, the single crystal silicon region 23a is electrically isolated.
For the SOI substrate thus fabricated, a high voltage element (not shown) is formed at a portion not surrounded by the silicon dioxide and another element is formed in the portion surrounded by the silicon dioxide to form a power IC.
In such conventional semiconductor device, in the process step illustrated in FIG. 1B, silicon dioxide layer 22 and the first single crystal silicon substrate 21 are ground simultaneously and subsequently abraded or polished. In such case, due to difference of hardness of the silicon dioxide and single crystal silicon, grinding speed is differentiated. Therefore, a step tends to be formed at an interface between the silicon dioxide layer 22 and the single crystal silicon substrate 21. Such step may cause formation of a void when the single crystal substrate 21 and the second single crystal substrate 23 are clad. Such void may cause failure, such as rupture or so forth during device fabrication. In the experiments performed by the inventors, it has been found that the height of the step becomes 500 .ANG. to 1000 .ANG., which increases possibility of formation of void.
Also, since the step 21a formed in the process step illustrated in FIG. 1A is steep, it concentration of stress at the step 21a is inherently caused upon formation of the silicon dioxide layer 22. Concentration of stress may cause defects in crystal. In TEM observation after anisotropic etching of the surface defect by the inventors, dislocation or stacking fault present at the interface between the silicon dioxide layer 22 and the single crystal silicon substrate 21 have been observed. The dislocation and/or stacking fault were presented in 10.sup.4 in number/cm.sup.2.
Furthermore, when the clad second single crystal silicon substrate is abraded and polished up to the predetermined thickness, the position of the interface between the second single crystal silicon substrate 23 and the first single crystal silicon substrate 21 (cladding surface) and the surface where the element is formed is reduced. This increases the possibility possibility that the element forming portion will be contaminated by pollutant in the atmosphere through the cladding surface.